1. Field
The following description relates to a semiconductor device fabricating technology, and, more particularly, to a method for fabricating a semiconductor device for a high voltage with a vertical channel. More particularly, the following description also relates to a method of fabricating a trench metal-oxide-semiconductor (MOS) transistor.
2. Description of Related Art
In a metal-oxide-semiconductor (MOS) transistor, such as a DMOS (double diffused MOS) transistor, which is mainly used as a semiconductor device for a high voltage, a channel is generally formed in a direction parallel to the surface of a substrate. However, recently, as the design rule of a semiconductor device decreases, a MOS transistor for a high voltage with a vertical channel to be advantageous in terms of high degree of integration, that is, a “trench MOS” transistor is becoming of greater concern. Describing briefly the structure of the trench MOS transistor, a drain is disposed on the lower surface of a substrate, a source is disposed on the upper surface of the substrate, and a gate electrode is disposed in a trench defined in the surface of the substrate. Current flows along the sidewalls of the trench in upward and downward directions of the substrate.
When designing the trench MOS transistor having the above-described structure, it is desirable to minimize a capacitance component to increase a switching speed. To this end, the present Applicants have disclosed “Trench MOSFET and Fabricating Method thereof” on Nov. 19, 2007 (see Korean Patent Laid-open Publication No. 10-2009-0051642). In the patent document, a diffused oxide layer is formed under a trench to have a width greater than the trench in an effort to minimize a capacitance component between a gate electrode and a drain region or a drift region, thereby increasing a switching speed. Hereafter, the fabricating method of the trench MOS transistor disclosed by the present applicant will be described with reference to FIG. 1.
FIG. 1 is a cross-sectional view illustrating a conventional trench MOS transistor.
Describing a conventional method for fabricating a trench MOS transistor with reference to FIG. 1, a trench 131 is defined by selectively etching a substrate 100 which includes an epi-layer 110 serving as a drain region (or a drift region) and a body layer 120. After forming spacers (not shown) on the sidewalls of the trench 131, a portion of the substrate 100, which is placed under the trench 131, is etched using the spacers as an etch barrier, and thereby, a groove (not shown) for forming a diffused oxide layer is defined. A diffused oxide layer 135, which has a width greater than the trench 131, is formed by performing a thermal oxidation process. After removing the spacers, a first gate oxide layer 132 is formed. A gate 130 is formed to fill the trench 131, and a source region 140, a contact region 150, a second gate oxide layer 160, and an upper metal 170 are formed.
In the conventional art, while the capacitance between the gate 130 and the epi-layer 110 serving as the drain region may be decreased by forming the diffused oxide layer 135 with the width greater than the trench 131, a problem is caused in that a switching speed decreases due to the capacitance between the gate 130 and the substrate 100 (actually, a drain). Also, because the width of the diffused oxide layer 135 disposed between the gate 130 and the substrate 100 is greater than that of the trench 131, a problem is caused in that the capacitance between them further increases.
Moreover, while thermal oxidation is used when forming the diffused oxide layer 135, due to the characteristics of the thermal oxidation in which an oxide layer grows from the surface of the substrate 100, a keyhole may be created in the diffused oxide layer 135 (see the reference symbol “A”), whereby the characteristics of a semiconductor device are likely to be degraded.